Peter Moceyunas

Title: Innovations by Peter Moceyunas in Circuit Design

Introduction

Peter Moceyunas is an accomplished inventor based in Los Altos, California. He has made significant contributions to the field of integrated circuit design. His innovative approach focuses on enhancing the efficiency of logical circuit synthesis.

Latest Patents

Peter Moceyunas holds a patent for the "Fast synthesis of logical circuit design with predictive timing." This invention involves a system that receives a logic design of a circuit for an integrated circuit and applies a reduced synthesis process. The reduced synthesis process is less computation-intensive compared to the optimized digital implementation synthesis process. It generates a netlist with suboptimal delay, which is then used in a timing analysis that alters standard delay computation to predict the timing of a fully optimized netlist. This method offers faster execution times while maintaining comparable performance, power, and area within a threshold of results generated by optimized digital implementation synthesis processes. He has 1 patent to his name.

Career Highlights

Peter Moceyunas is currently employed at Synopsys, Inc., where he continues to push the boundaries of circuit design technology. His work has been instrumental in developing more efficient synthesis processes that benefit the industry.

Collaborations

Throughout his career, Peter has collaborated with notable colleagues, including Jiong Luo and Luca Gaetano Amaru. These partnerships have fostered innovation and contributed to advancements in circuit design.

Conclusion

Peter Moceyunas exemplifies the spirit of innovation in the field of integrated circuit design. His contributions, particularly in the area of logical circuit synthesis, have paved the way for more efficient and effective design processes.