Allen, TX, United States of America

Paul J Lewis

This inventor holds 1 USPTO granted patent and 1 published patent application and 1 EPO patent. Top assignee: Raytheon Company. Active years: 2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Paul J Lewis. Retrieved from https://idiyas.com/inventor/paul-j-lewis-g3aj2soi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

 

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2019

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1 patent (USPTO):Explore Patents

Title: Paul J. Lewis: FPGA Control Through Ethernet

Introduction

Paul J. Lewis is an inventor associated with Allen, Texas, and Raytheon Company. His patent work addresses a way to control a field-programmable gate array (FPGA) over Ethernet by translating network packets into register operations.

Latest Patents

The available information identifies 1 patent associated with Lewis: “System and Method for Address-Mapped Control of Field Programmable Gate Array (FPGA) via Ethernet.” The invention describes receiving Ethernet packets containing FPGA control or status information, removing Ethernet and UDP headers, and using UDP metadata to convert the packets into read or write messages for FPGA registers. The FPGA then performs the requested register operations.

Career Highlights

Lewis’s listed patent connects network communication with hardware control, enabling Ethernet messages to support reads and writes to FPGA registers. The patent is associated with Raytheon Company.

Collaborations

The provided information lists Brandon H. Daugherty and Brian D. Sirois as Lewis’s coworkers. It does not specify their roles in the patent.

Conclusion

Paul J. Lewis’s listed invention focuses on address-mapped FPGA control over Ethernet, translating network packets into register-level operations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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