San Jose, CA, United States of America

Patrick J Lord

USPTO Granted Patents = 1 

Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2017

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1 patent (USPTO):

Title: Innovations of Patrick J Lord in Photoresist Strip Processes

Introduction

Patrick J Lord is an accomplished inventor based in San Jose, CA. He has made significant contributions to the field of semiconductor manufacturing, particularly in the area of photoresist strip processes. His innovative methods aim to enhance device integrity in silicon wafers and other substrates.

Latest Patents

Patrick J Lord holds a patent for "Photoresist strip processes for improved device integrity." This patent outlines methods and apparatus for hydrogen-based photoresist strip operations that effectively reduce dislocations in silicon wafers. The techniques described in the patent include minimizing the hydrogen budget, providing dilute hydrogen concentrations, controlling process conditions, and performing post-strip venting processes. His work in this area has the potential to significantly improve the quality and reliability of semiconductor devices.

Career Highlights

Patrick is currently associated with Novellus Systems Incorporated, a company known for its advanced semiconductor manufacturing equipment. His role at Novellus has allowed him to apply his expertise in developing innovative solutions that address critical challenges in the industry.

Collaborations

Throughout his career, Patrick has collaborated with notable professionals in the field, including Roey Shaviv and Kirk J Ostrowski. These collaborations have contributed to the advancement of technologies in semiconductor manufacturing.

Conclusion

Patrick J Lord's contributions to photoresist strip processes exemplify his commitment to innovation in the semiconductor industry. His patent and collaborative efforts reflect a dedication to improving device integrity and advancing manufacturing techniques.

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