Stroudsburg, PA, United States of America

Patricia J Leith

This inventor holds 1 USPTO granted patent. Top assignee: Agere Systems Inc.. Active years: 2012.


% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2012

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1 patent (USPTO):Explore Patents

Title: Patricia J Leith: Innovator in Integrated Circuit Technology

Introduction

Patricia J Leith is a notable inventor based in Stroudsburg, PA (US). She has made significant contributions to the field of integrated circuit technology. With a focus on chip identification, her work has implications for the future of semiconductor design and functionality.

Latest Patents

Leith holds a patent for "Chip identification using top metal layer." This innovative integrated circuit (IC) structure includes a semiconductor substrate with a plurality of memory bits that contain IC identification information. The design features alternating metal and via layers above the substrate, along with a bond pad layer formed over the top metal layer. This bond pad layer consists of multiple pins connected to the memory bits, facilitating the programming of IC identification information.

Career Highlights

Patricia J Leith has worked at Agere Systems Inc., where she has been instrumental in advancing integrated circuit technologies. Her patent reflects her expertise and dedication to innovation in the semiconductor industry.

Collaborations

Throughout her career, Leith has collaborated with notable colleagues, including Edward Belden Harris and Lyle K Mantz, II. These partnerships have contributed to her success and the development of cutting-edge technologies.

Conclusion

Patricia J Leith's contributions to integrated circuit technology exemplify her innovative spirit and commitment to advancing the field. Her patent on chip identification showcases her expertise and the potential for future developments in semiconductor design.

Profile summary based on public USPTO records.
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