Company Filing History:
Years Active: 2008
Title: The Innovative Contributions of Parthasarathy Rajagopalan
Introduction
Parthasarathy Rajagopalan is a notable inventor based in Milpitas, California. He has made significant contributions to the field of integrated circuits, particularly through his innovative patent that addresses critical challenges in the manufacturing process.
Latest Patents
Rajagopalan holds a patent titled "Method and apparatus for avoiding dicing chip-outs in integrated circuit die." This invention provides a method and apparatus that includes several steps: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw. This patent showcases his expertise in enhancing the reliability and efficiency of integrated circuit production.
Career Highlights
Rajagopalan is associated with LSI Logic Corporation, where he has contributed to various projects and innovations in the semiconductor industry. His work has been instrumental in advancing technologies that are crucial for modern electronic devices.
Collaborations
Throughout his career, Rajagopalan has collaborated with several talented individuals, including Zafer S Kutlu and Emery O Sugasawara. These collaborations have fostered an environment of innovation and creativity, leading to impactful advancements in their field.
Conclusion
Parthasarathy Rajagopalan's contributions to the field of integrated circuits through his patent and work at LSI Logic Corporation highlight his role as a significant inventor. His innovative methods continue to influence the semiconductor industry and improve manufacturing processes.