The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2008
Filed:
May. 18, 2005
Parthasarathy Rajagopalan, Milpitas, CA (US);
Zafer Kutlu, Menlo Park, CA (US);
Emery O. Sugasawara, Pleasanton, CA (US);
Charles E. Vonderach, Livermore, CA (US);
Dilip P. Vijay, Redwood City, CA (US);
Yogendra Ranade, Fremont, CA (US);
Jeff Hall, San Jose, CA (US);
Dwight Manning, San Jose, CA (US);
Parthasarathy Rajagopalan, Milpitas, CA (US);
Zafer Kutlu, Menlo Park, CA (US);
Emery O. Sugasawara, Pleasanton, CA (US);
Charles E. Vonderach, Livermore, CA (US);
Dilip P. Vijay, Redwood City, CA (US);
Yogendra Ranade, Fremont, CA (US);
Jeff Hall, San Jose, CA (US);
Dwight Manning, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile