Trojanovice, Czechia

Ondrej Picha

This inventor holds 1 USPTO granted patent. Top assignee: Semiconductor Components Industries, LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ondrej Picha. Retrieved from https://idiyas.com/inventor/ondrej-picha

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Ondrej Picha and His Patent in Semiconductor Modeling.

Introduction

Ondrej Picha is an inventor associated with Trojanovice, Czech Republic, and Semiconductor Components Industries, LLC. His patent work includes a method for generating product system models for system-level simulators.

Latest Patents

Picha is associated with 1 patent: “Automated Power Discrete and Module Model Generation for System Level Simulators.” The invention describes a process for generating a product system model. A user selects a product type, and the system retrieves an associated SPICE model from a database. The user then specifies a process condition, system and operating characteristics, and circuit characteristics. A simulation module generates SPICE model output, which a formatting module converts into a product system model file. The file may be structured text, plain text, or delimited text.

Career Highlights

Picha’s patent focuses on streamlining the creation of models for power discrete products and modules. By combining user-provided parameters, SPICE simulation, and file formatting, the method supports the preparation of product models for system-level simulation.

Collaborations

Picha’s listed coworkers include Yun Peng Xiao and James Joseph Victory. The patent’s development reflects work in semiconductor modeling and simulation.

Conclusion

Ondrej Picha’s patent describes a practical workflow for turning product and circuit specifications into system-level model files, connecting semiconductor device simulation with broader system design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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