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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Norman M Hayes

This inventor holds 12 USPTO granted patents. Top assignees: Sun Microsystems, Inc., Xerox Corporation. Active years: 1994-2000.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Norman M Hayes. Retrieved from https://idiyas.com/inventor/norman-m-hayes

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 10

Forward Citations = 298(Granted Patents)


Company Filing History:

goldMedal12 out of 7,642 
 
Sun Microsystems, Inc.
 patents
silverMedal1 out of 24,257 
 
Xerox Corporation
 patents
where one patent can have more than one assignee

Years Active: 1994-2000

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12 patents (USPTO):Explore Patents
1. 6073212 - Reducing bandwidth and areas needed for non-inclusive memory hierarchy (2000-06-06),
2. 6065097 - Apparatus and method for sharing a unified memory bus between external (2000-05-16),
3. 5987570 - Performing overlapping burst memory accesses and interleaved memory (1999-11-16),
4. 5909697 - Reducing cache misses by snarfing writebacks in non-inclusive memory (1999-06-01),
5. 5781721 - Method and apparatus for testing cache RAM residing on a microprocessor (1998-07-14),
6. 5708792 - Method and apparatus for a coherent copy-back buffer in a multipressor (1998-01-13),
7. 5675765 - Cache memory system with independently accessible subdivided cache tag (1997-10-07),
8. 5497480 - Broadcast demap for deallocating memory pages in a multiprocessor system (1996-03-05),
9. 5440707 - Instruction and data cache with a shared TLB for split accesses and (1995-08-08),
10. 5353426 - Cache miss buffer adapted to satisfy read requests to portions of a (1994-10-04),
11. 5353425 - Methods and apparatus for implementing a pseudo-LRU cache memory (1994-10-04),
12. 5329627 - Method and apparatus for a translation lookaside buffer with built-in (1994-07-12),

Title: Innovator Spotlight: Norman M. Hayes

Introduction

Norman M. Hayes is a prominent inventor based in Sunnyvale, California, recognized for his significant contributions to technology with 12 patents to his name. His work primarily focuses on optimizing memory hierarchy and enhancing computer system efficiencies, particularly within cache memory systems.

Latest Patents

One of his latest innovations is a method for reducing bandwidth and the areas needed for non-inclusive memory hierarchy. This invention presents an apparatus designed to optimize a non-inclusive hierarchical cache memory system featuring a first and second cache organized in a hierarchical structure.

The first and second caches operate in conjunction with a dual directory that holds tags and states of the level two cache. This setup allows for more efficient handling of snoop requests, ultimately reducing bandwidth appropriation and improving performance. In addition, his work includes an innovative apparatus for sharing a unified memory bus between external caches and primary memory, which further streamlines access during data operations.

Career Highlights

Throughout his career, Norman has made impactful contributions while working with renowned companies, including Sun Microsystems, Inc. and Xerox Corporation. His experience at these firms has significantly influenced his approach to technology and innovation.

Collaborations

During his journey in the tech landscape, he has had the opportunity to collaborate with talented individuals such as Adam C. Malamy and Rajiv N. Patel. These collaborations have helped foster innovation and push the boundaries of technology further.

Conclusion

Norman M. Hayes exemplifies an innovative spirit within the tech industry. With his extensive patent portfolio and contributions to memory optimization, he continuously influences the field, inspiring future generations of inventors. His achievements not only highlight his expertise but also demonstrate the importance of collaboration in driving technological advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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