Dresden, Germany

Norbert Labrenz

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Infineon Technologies Austria Ag. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Norbert Labrenz. Retrieved from https://idiyas.com/inventor/norbert-labrenz

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Norbert Labrenz and Semiconductor Device Innovation.

Introduction

Norbert Labrenz is an inventor associated with Dresden, Germany, and Infineon Technologies Austria AG. His patent work concerns semiconductor device design and manufacturing.

Latest Patents

Labrenz is credited with 1 patent: “Semiconductor Device Having an Isolation Region with a Recess and Method of Manufacturing the Semiconductor Device.” The invention describes a substrate with an isolation region containing a recess, where an active or passive device is formed. The device includes two semiconductor material regions that adjoin in a direction parallel to the substrate’s main surface, with their upper surfaces at different heights. This arrangement offers a specific structural approach to integrating device regions within a semiconductor substrate.

Career Highlights

Labrenz’s listed patent reflects work in semiconductor technology, particularly device structures and manufacturing methods. His professional association with Infineon Technologies Austria AG connects his work to a company active in the semiconductor industry.

Collaborations

Alim Karmous is identified as Labrenz’s coworker. The available information does not specify whether they collaborated on this patent or other projects.

Conclusion

Norbert Labrenz’s recorded invention addresses the structure and manufacture of a semiconductor device with a recessed isolation region, highlighting his contribution to semiconductor innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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