Fukuoka, Japan

Nobuhisa Nakashima

This inventor holds 5 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Corporation. Active years: 1992-2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nobuhisa Nakashima. Retrieved from https://idiyas.com/inventor/nobuhisa-nakashima

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 2

Forward Citations = 14(Granted Patents)


Location History:

  • Tokyo, JP (2005)
  • Fukuoka, JP (1992 - 2007)

Company Filing History:


Years Active: 1992-2007

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5 patents (USPTO):Explore Patents

Title: Nobuhisa Nakashima: Semiconductor Device Inventor

Introduction

Nobuhisa Nakashima is an inventor associated with Fukuoka, Japan, whose work includes semiconductor device technologies. He is credited with 5 patents.

Latest Patents

One of Nakashima’s latest patents concerns a semiconductor element with layers of different conductivity types. Its design includes electrode layers connected along an inclined surface, an insulating layer, and a recessed portion in at least one semiconductor layer. These features describe the structure and arrangement of components within the device.

Another patent describes a pressure-contact-type semiconductor device with dummy segments. Insulating layers cover protruding portions of the outermost and innermost segments, with a clearance between the insulation and a cathode strain-relief plate. The other segments have cathode electrodes sized to contact the plate.

Career Highlights

Nakashima’s listed company affiliations include Mitsubishi Denki Kabushiki Kaisha and Mitsubishi Electric Corporation. His patent work reflects a focus on semiconductor elements and device construction.

Collaborations

Nakashima’s listed coworkers include Tokumitsu Sakamoto and Yuzuru Konishi.

Conclusion

Nobuhisa Nakashima’s patent portfolio highlights contributions to semiconductor device design, including layered semiconductor elements and pressure-contact structures.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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