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For the Inventor, By the Inventor

Redmond, WA, United States of America

Neeraj Upasani

This inventor holds 18 USPTO granted patents and 4 published patent applications and 1 EPO patent. Top assignee: Meta Platforms, Inc.. Active years: 2021-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Neeraj Upasani. Retrieved from https://idiyas.com/inventor/neeraj-upasani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 

% Patents Active = 94.4

 

Average Co-Inventor Count = 3.6

ph-index = 2

Forward Citations = 26(Granted Patents)


Location History:

  • Redmond, WA (US) (2021 - 2023)
  • Sammamish, WA (US) (2022 - 2024)

Company Filing History:

goldMedal18 out of 9,904 
 
Meta Platforms, Inc.
 patents

Years Active: 2021-2025

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18 patents (USPTO):Explore Patents
1. 12299183 - Tamper detection and prevention in computer systems having one-time programmable memory (2025-05-13),
2. 12200130 - ROM instruction authentication and integrity verification for artificial reality security controller (2025-01-14),
3. 11948654 - Distributed phased SRAM repair for systems on a chip (2024-04-02),
4. 11941131 - Isolation of secrets from an operating system (2024-03-26),
5. 11775448 - System on a chip (SOC) communications to prevent direct memory access (DMA) attacks (2023-10-03),
6. 11755747 - High throughput storage encryption (2023-09-12),
7. 11637916 - Inline encryption of packet data in a wireless communication system (2023-04-25),
8. 11636210 - Artificial reality system with multi-stage boot process (2023-04-25),
9. 11601532 - Wireless communication with code separation (2023-03-07),
10. 11520707 - System on a chip (SoC) communications to prevent direct memory access (DMA) attacks (2022-12-06),
11. 11474970 - Artificial reality system with inter-processor communication (IPC) (2022-10-18),
12. 11470061 - Parallel scheduling of encryption engines and decryption engines to prevent side channel attacks (2022-10-11),
13. 11449606 - Monitoring circuit including cascaded s-boxes for fault injection attack protection (2022-09-20),
14. 11423152 - Randomized clock cycle lengths for boot sequences (2022-08-23),
15. 11277255 - Swapping of encryption and decryption operations for side channel attack protection (2022-03-15),

Title: The Innovative Journey of Neeraj Upasani

Introduction:

Neeraj Upasani, a talented inventor based in Redmond, WA, has made significant contributions to the field of technology through his innovative creations and patents.

Latest Patents:

Neeraj Upasani's latest patents include groundbreaking inventions in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his commitment to driving progress in these fields.

Career Highlights:

With a career spanning over two decades, Neeraj Upasani has worked with leading tech companies, research institutions, and universities, honing his skills and expertise in developing cutting-edge solutions that have the potential to shape the future.

Collaborations:

Throughout his career, Neeraj Upasani has collaborated with top engineers, scientists, and researchers, fostering a culture of innovation and knowledge-sharing that has led to the successful development of revolutionary technologies.

Conclusion:

Neeraj Upasani's passion for innovation, coupled with his dedication to pushing the boundaries of technology, continues to inspire the next generation of inventors and entrepreneurs to pursue their dreams and create a better tomorrow.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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