Navnit K Nanda

Title: Innovations of Navnit K Nanda

Introduction

Navnit K Nanda is a notable inventor based in Jammu, India. He has made significant contributions to the field of electronics, particularly in the area of delay testing for LSI circuit faults. His innovative approach has the potential to enhance the reliability and efficiency of combinational logic circuits.

Latest Patents

Navnit K Nanda holds a patent for "Simplified delay testing for LSI circuit faults." This patent describes a method for thorough delay testing of a combinational logic circuit by changing only one input at a time and checking the output shortly thereafter. The invention includes arrangements for systematically applying all possible single transitions of binary input signals to the circuit. An economical test circuit is proposed, utilizing a conventional binary counter and an associated ring counter to generate test signals, along with input switching circuits or multiplexers for steering data to the logic being tested.

Career Highlights

Navnit K Nanda is affiliated with the University of Southern California, where he continues to contribute to research and development in his field. His work has garnered attention for its practical applications in improving circuit testing methodologies.

Collaborations

He has collaborated with Melvin A Breuer, further enhancing the scope and impact of his research efforts.

Conclusion

Navnit K Nanda's innovative work in delay testing for LSI circuits exemplifies the importance of advancements in electronic testing methods. His contributions are paving the way for more reliable electronic systems.