Berwyn, PA, United States of America

Naresh Gupta

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Agere Systems Guardian Corp.. Active years: 2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Naresh Gupta. Retrieved from https://idiyas.com/inventor/naresh-gupta

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2002

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1 patent (USPTO):Explore Patents

Title: Naresh Gupta: Innovator in Phase-Locked Loop Technology

Introduction

Naresh Gupta is a notable inventor based in Berwyn, PA (US). He has made significant contributions to the field of electronics, particularly in the area of phase-locked loops (PLLs). His innovative work has led to the development of a patent that addresses critical issues in counter operations.

Latest Patents

Naresh Gupta holds a patent titled "Methods and devices for testing the operation of counters used in phase-locked loops." This patent focuses on precisely measuring intermittent miscounts generated by counters in a PLL. The method involves detecting changes to a predetermined waveform, such as a sawtooth waveform. Miscounts are identified using an open loop setup, which includes two separate signal generators feeding distinct frequencies into the MAIN and REF counters of a PLL. By slightly offsetting the frequencies and integrating the output, a predetermined waveform is generated. Miscounts can then be detected by comparing the waveforms corresponding to miscounts with theoretically predicted, predetermined waveforms. This innovative approach enhances the reliability of PLL systems.

Career Highlights

Naresh Gupta has had a successful career, working at Agere Systems Guardian Corp. His expertise in electronics and signal processing has positioned him as a valuable asset in his field. His contributions have not only advanced technology but have also paved the way for further innovations in PLL applications.

Collaborations

Throughout his career, Naresh has collaborated with notable colleagues, including David Loren Anderson and Thomas L. Shewell. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.

Conclusion

Naresh Gupta's work in the field of phase-locked loops exemplifies the impact of innovative thinking in technology. His patent addresses significant challenges in counter operations, showcasing his dedication to advancing electronic systems. His contributions continue to influence the industry and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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