Inagi, Japan

Naonobu Sukegawa

This inventor holds 21 USPTO granted patents and 2 published patent applications, primarily in Multiprocessor Systems. Top assignee: Hitachi, Ltd.. Active years: 1997-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Naonobu Sukegawa. Retrieved from https://idiyas.com/inventor/naonobu-sukegawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 57.1

Average Co-Inventor Count = 2.2

ph-index = 10

Forward Citations = 516(Granted Patents)


Location History:

  • Kokubunji, JP (1997 - 2001)
  • Hadano, JP (1999 - 2001)
  • Tokyo, JP (2007)
  • Inagi, JP (2002 - 2012)

Company Filing History:


Years Active: 1997-2012

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Areas of Expertise:
Multiprocessor
Cache Memory
Power Management
Parallel Processing
Job Scheduling
Data Communication
Synchronization
Execution Code
Heterogeneous Systems
Control Method
Memory Access
21 patents (USPTO):Explore Patents

Title: **Naonobu Sukegawa: Innovator in Multiprocessor Technology**

Introduction

Naonobu Sukegawa, an esteemed inventor based in Inagi, Japan, has made significant strides in the field of computer systems and processor technology. With an impressive portfolio of 21 patents, Sukegawa is recognized for his innovative approaches to optimizing code generation and processor design for multiprocessor systems.

Latest Patents

Among his latest innovations is the "Optimum Code Generation Method and Compiler Device for Multiprocessor." This invention introduces a method for generating optimal parallel codes from source code designed for computer systems with multiple processors sharing cache or main memory. The method involves analyzing operation amounts and process contents to differentiate between dependent and independent processes, ultimately facilitating efficient code execution.

In addition, he holds a patent for a "Processor Having a Cache Memory Comprised of a Plurality of Large Scale Integration." This invention provides a streamlined approach to constructing processors using multiple large-scale integrations (LSIs). The design includes a first LSI as the processor and a second LSI with cache memory, linked by information transmission paths that help monitor cache hits through a sophisticated address information broadcasting and comparison system.

Career Highlights

Sukegawa's contributions to Hitachi, Ltd., showcase his expertise in developing cutting-edge technologies that enhance computer performance and efficiency. His inventions not only demonstrate a deep understanding of computer architectures but also reflect his commitment to advancing multiprocessor functionality.

Collaborations

Throughout his career, Naonobu Sukegawa has collaborated with notable colleagues, including Hiroaki Fujii and Masaaki Shimizu. This teamwork has fostered a creative environment that encourages innovation and leads to groundbreaking advancements in technology.

Conclusion

Naonobu Sukegawa's legacy as an inventor continues to grow with each patent, representing a profound impact on the fields of computer science and engineering. His work is set to influence future technological developments, particularly in the realm of multiprocessor systems and efficient code generation methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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