Nan-Chi Chou

Title: The Innovations of Nan-Chi Chou

Introduction

Nan-Chi Chou is a notable inventor based in Fremont, CA (US). He has made significant contributions to the field of field programmable gate arrays (FPGAs). With a total of 2 patents, his work focuses on enhancing the performance of memory modules implemented on FPGA devices.

Latest Patents

One of his latest patents is titled "Memory re-implementation for field programmable gate arrays." This invention involves re-implementing memory modules on an FPGA device to improve performance, particularly in reducing logic delays. The process includes selecting one or more logic blocks that realize the logic function of a memory module. A timing analysis is conducted to identify the most critical signal pin of the selected logic blocks. The patent discloses methods for deriving memory module re-implementation for various types of critical pins. It also describes procedures for integrating physical timing analysis, memory transformation, placement, and routing, along with the selection of logic blocks for re-implementation.

Career Highlights

Throughout his career, Nan-Chi Chou has demonstrated a strong commitment to innovation in the field of electronics. His work has contributed to advancements in FPGA technology, which is crucial for various applications in computing and digital systems.

Collaborations

Nan-Chi has collaborated with notable colleagues, including Peter Ramyalal Suaris and Lung-Tien Liu. Their combined expertise has furthered the development of innovative solutions in the field.

Conclusion

Nan-Chi Chou's contributions to the field of field programmable gate arrays exemplify the impact of innovation in technology. His patents reflect a deep understanding of memory performance and logic optimization.