The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2010
Filed:
Jun. 22, 2007
Peter Ramyalal Suaris, Camas, WA (US);
Lung-tien Liu, Encinitas, CA (US);
Yuzheng Ding, Berkeley Heights, NJ (US);
Nan-chi Chou, Fremont, CA (US);
Peter Ramyalal Suaris, Camas, WA (US);
Lung-Tien Liu, Encinitas, CA (US);
Yuzheng Ding, Berkeley Heights, NJ (US);
Nan-Chi Chou, Fremont, CA (US);
Other;
Abstract
Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.