Naifeng Jing

Title: Naifeng Jing: Innovator in FPGA Technology

Introduction

Naifeng Jing is a prominent inventor based in Shanghai, China. He has made significant contributions to the field of Field Programmable Gate Arrays (FPGAs). His innovative work focuses on enhancing the reliability and efficiency of FPGA designs.

Latest Patents

Naifeng Jing holds a patent for "In-place resynthesis and remapping techniques for soft error mitigation in FPGA." This patent addresses the challenges of single event upsets (SEUs) in static memory (SRAM) based FPGAs. The techniques described in the patent include in-place reconfiguration (IPR), in-place X-filling (IPF), and in-place inversion (IPV). These methods allow for the reconfiguration of Look-Up Table (LUT) functions without the need for rerouting, thus improving FPGA designs with low overhead. Additionally, for FPGAs with decomposable LUT architectures, an in-place decomposition (IPD) method is introduced, which remaps LUT functions into smaller functions. This leverages unused outputs of the LUT and utilizes built-in hard macros in programmable-logic blocks (PLBs). The methods can be applied in-place to mapped circuits before or after routing, ensuring that placement, routing, and design closure remain unaffected.

Career Highlights

Naifeng Jing is affiliated with the University of California, where he continues to advance research in FPGA technology. His work has garnered attention for its practical applications in mitigating soft errors in electronic systems.

Collaborations

Naifeng has collaborated with notable colleagues, including Lei He and Ju-Yueh Lee. Their combined expertise has contributed to the development of innovative solutions in the field of FPGA design.

Conclusion

Naifeng Jing's contributions to FPGA technology through his patent and research efforts highlight his role as a key innovator in the field. His work not only addresses critical challenges but also paves the way for future advancements in electronic design.