San Jose, CA, United States of America

Na Xing


Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 14(Granted Patents)


Company Filing History:


Years Active: 2015

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1 patent (USPTO):Explore Patents

Title: Na Xing - Innovator in Design Verification Workstations

Introduction

Na Xing is a notable inventor based in San Jose, California. He has made significant contributions to the field of design verification, particularly through his innovative patent. His work focuses on enhancing the efficiency and effectiveness of design verification processes.

Latest Patents

Na Xing holds a patent for the "Development and debug environment in a constrained random verification." This invention describes a design verification workstation that integrates both debug and constraint solver capabilities during the simulation of a design under test. The workstation allows users to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the-fly during the simulation. This process eliminates the need for recompiling the test case, streamlining the verification process. Once users are satisfied with their modifications, they can save these changes for future use.

Career Highlights

Na Xing is currently employed at Synopsys, Inc., a leading company in electronic design automation. His role involves developing advanced tools that facilitate design verification, making significant strides in the industry. His innovative approach has garnered attention and respect among his peers.

Collaborations

Na Xing collaborates with talented individuals such as Dhiraj Goswami and Aijun Hu, who contribute to the dynamic environment at Synopsys, Inc. Their teamwork fosters creativity and innovation in the development of cutting-edge design verification solutions.

Conclusion

Na Xing's contributions to design verification through his patent and work at Synopsys, Inc. highlight his role as an influential inventor in the technology sector. His innovative solutions continue to shape the future of design verification processes.

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