Karnataka, India

Murali Krishna Balaga

This inventor holds 1 USPTO granted patent. Top assignee: Sandisk Technologies Inc.. Active years: 2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Murali Krishna Balaga. Retrieved from https://idiyas.com/inventor/murali-krishna-balaga

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 17(Granted Patents)


Company Filing History:


Years Active: 2019

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1 patent (USPTO):Explore Patents

Title: Murali Krishna Balaga: Innovator in Duty Cycle Correction

Introduction

Murali Krishna Balaga is a notable inventor based in Karnataka, India. He has made significant contributions to the field of electronics, particularly in the area of duty cycle correction. His innovative approach has led to the development of a unique circuit that addresses duty cycle errors in clock signals.

Latest Patents

Murali Krishna Balaga holds a patent for a "Duty cycle correction scheme." This invention involves control circuitry that determines a duty cycle error for a sample clock signal. Based on this error, the control circuitry identifies a corrective direction to adjust the duty cycle. The selection circuitry, guided by a selection signal, chooses between leading and lagging phase signals. Ultimately, the output circuitry combines these signals to generate an output clock signal with the desired duty cycle.

Career Highlights

Murali Krishna Balaga is currently employed at SanDisk Technologies Inc., where he continues to innovate and contribute to advancements in technology. His work has been instrumental in enhancing the performance of electronic devices through improved clock signal management.

Collaborations

He has collaborated with talented coworkers, including Bhawna Tomar and Ajay Kanth Chitturi, who share his passion for innovation and technology.

Conclusion

Murali Krishna Balaga's contributions to duty cycle correction demonstrate his commitment to advancing electronic engineering. His patent reflects a significant step forward in improving clock signal accuracy, showcasing his innovative spirit and technical expertise.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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