Fort Collins, CO, United States of America

Mona D Rideout

This inventor holds 1 USPTO granted patent. Top assignee: Xilinx, Inc.. Active years: 2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mona D Rideout. Retrieved from https://idiyas.com/inventor/mona-d-rideout

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2012

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1 patent (USPTO):Explore Patents

Title: Mona D. Rideout and Automated Timing-Constraint Generation.

Introduction

Mona D. Rideout is an inventor associated with Fort Collins, Colorado, and Xilinx, Inc. Her patent work addresses the automatic creation of timing constraints for electronic design interfaces.

Latest Patents

Rideout is named on one patent, “Apparatus and Method for Automated Determination of Timing Constraints.” The invention uses a graphical user interface to collect timing parameters for input interfaces and automatically generate corresponding timing constraints. It displays the generated constraints for review or modification, helping designers analyze interfaces without having to define constraint-language parameters manually or possess detailed knowledge of the constraint language.

Career Highlights

Rideout’s recorded patent contribution focuses on making the definition of timing constraints more accessible and reducing the risk of errors in interface specifications. Her work is associated with Xilinx, Inc., a company known for programmable logic and semiconductor technologies.

Collaborations

The supplied information lists Scott J. Campbell and Paul J. Glairon as Rideout’s coworkers. Their names are provided as professional associations, though the available details do not specify their roles in the patent.

Conclusion

Mona D. Rideout’s patent describes an automated approach to generating and reviewing timing constraints, supporting more efficient and reliable analysis of electronic design interfaces.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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