Bengaluru, India

Mohammed Zuber P Malek

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Qualcomm Incorporated. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mohammed Zuber P Malek. Retrieved from https://idiyas.com/inventor/mohammed-zuber-p-malek

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Mohammed Zuber P Malek and Memory Patching Innovation.

Introduction

Mohammed Zuber P Malek is an inventor based in Bengaluru, India, and is associated with Qualcomm Incorporated. His work includes an invention focused on reducing latency during memory patching.

Latest Patents

Malek is associated with 1 patent: “Memory Mirror Sequencing for Reduced Latency in Memory Patching.” The patent describes initializing a memory mirror sequence controller to coordinate parallel read-only memory (ROM) to random-access memory (RAM) copy operations. The controller uses parallelization parameters to trigger the copy procedure, after which a memory-patching process updates selected RAM contents for an updated built-in self-test (BIST) test pattern. This approach is intended to make memory patching more efficient by reducing latency.

Career Highlights

Malek’s listed patent work concerns memory systems and the sequencing of parallel ROM-to-RAM copy operations. His association with Qualcomm Incorporated places this work within the company’s technology and innovation activities.

Collaborations

The provided information lists Rajesh Kumar Tiwari and Chintakrindi Bhavana as Malek’s coworkers. Their specific roles in the patent or related work are not specified.

Conclusion

Mohammed Zuber P Malek’s patent describes a memory mirror sequencing approach that coordinates parallel copying and patching to reduce latency and support updated BIST test patterns.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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