Hsinchu, Taiwan

Ming-Mao Chiang

This inventor holds 1 USPTO granted patent. Top assignee: Silicon Integrated Systems Corporation. Active years: 2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ming-Mao Chiang. Retrieved from https://idiyas.com/inventor/ming-mao-chiang-ynlr8tvy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2004

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1 patent (USPTO):Explore Patents

Title: Ming-Mao Chiang and CMOS Process Optimization.

Introduction

Ming-Mao Chiang is an inventor based in Hsinchu, Taiwan. His patent work addresses semiconductor manufacturing and the optimization of multi-threshold voltage CMOS processes.

Latest Patents

Chiang is associated with 1 patent: “Method for Multi-Threshold Voltage CMOS Process Optimization.” The invention describes a process for assigning devices to different threshold-voltage categories using timing analysis. It establishes timing models, generates a static timing analysis report, and classifies devices according to their setup-time margins. Devices with smaller margins can be changed to low-threshold devices, while those with larger margins can be changed to high-threshold devices. The method then checks device setup times and applies separate pocket implant processes for normal-, low-, and high-threshold devices.

Career Highlights

Chiang is associated with Silicon Integrated Systems Corporation. His patent reflects work on coordinating circuit timing requirements with semiconductor process steps.

Collaborations

The provided information names Chin-Cho Tsai and Tien-Yueh Liu as Chiang’s coworkers. It does not specify their roles in the patent or whether they collaborated on it.

Conclusion

Ming-Mao Chiang’s documented invention combines static timing analysis and threshold-voltage device selection to support CMOS process optimization.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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