Hyderabad, India

Mehul Jitendrabhai Vora

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Advanced Micro Devices Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mehul Jitendrabhai Vora. Retrieved from https://idiyas.com/inventor/mehul-jitendrabhai-vora

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Mehul Jitendrabhai Vora: Patent Inventor in DMA Failure Detection

Introduction

Mehul Jitendrabhai Vora is an inventor based in Hyderabad, India, and works at Advanced Micro Devices Corporation. His patent work addresses failure detection and resource handling in transport offload systems.

Latest Patents

The provided information lists 1 patent associated with Vora: “Host-Facing DMA Failure Detection for Transport Offload with Multi-Stage Queue Operations.” The invention describes using error-indicating bits in a task pointer, such as a work queue element (WQE), to notify a downstream queue or pipeline when an upstream stage detects a failed direct memory access (DMA) operation. The downstream stage can then handle the error and reclaim resources allocated to the WQE, including an intermediate buffer.

Career Highlights

Vora’s listed patent focuses on communicating DMA failures across successive stages of a transport offload pipeline. By placing error indicators in WQEs passed between queues, the described approach enables downstream stages to recognize upstream failures and take appropriate recovery actions.

Collaborations

The provided information names Sanjay Shanbhogue and Murty Kotha as Vora’s coworkers. Their specific roles in the patent or related work are not stated.

Conclusion

Mehul Jitendrabhai Vora’s listed invention addresses a practical challenge in multi-stage transport offload by signaling DMA failures between pipeline stages and supporting downstream resource recovery.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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