Location History:
- Santa Clara, CA (US) (2017)
- Federal Way, WA (US) (2017)
Company Filing History:
Years Active: 2017
Title: Meera Ganesan: Innovator in Memory Subsystem Technologies
Introduction
Meera Ganesan is a prominent inventor based in Santa Clara, CA, known for her contributions to memory subsystem technologies. With a total of 2 patents, she has made significant advancements in error management and data handling within memory systems. Her work is instrumental in enhancing the reliability and efficiency of memory resources.
Latest Patents
Ganesan's latest patents include innovative solutions for dynamically changing lockstep configurations and methods for handling data error events with a memory controller. The first patent focuses on a memory subsystem that enables dynamically changing lockstep partnerships to spread error correction across memory resources. This technology allows for the cancellation or reversal of lockstep partnerships in response to detected hard errors, thereby creating new partnerships to maintain system integrity.
The second patent outlines techniques for error detection and correction in memory systems that include spare memory segments. This invention describes a memory controller that performs scrubbing operations to detect errors in active memory segments while also managing spare segments for potential activation. The dual-handler process ensures that only specific error events lead to platform crashes, enhancing overall system reliability.
Career Highlights
Meera Ganesan is currently employed at Intel Corporation, where she continues to innovate in the field of memory technologies. Her work at Intel has positioned her as a key player in developing advanced memory solutions that address critical challenges in data integrity and error management.
Collaborations
Throughout her career, Ganesan has collaborated with notable colleagues, including Anil Agrawal and Satish Muthiyalu. These collaborations have fostered a creative environment that encourages the development of cutting-edge technologies in memory systems.
Conclusion
Meera Ganesan's contributions to memory subsystem technologies through her patents and work at Intel Corporation highlight her role as a leading innovator in the field. Her advancements in error management and data handling are paving the way for more reliable memory systems in the future.