This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Waseda University. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Masashi Tawada: Inventor in Ising Model Computation
Introduction
Masashi Tawada is an inventor based in Tokyo, Japan, associated with Waseda University. His patent work addresses computational methods for reducing the bit-width used in an Ising model.
Latest Patents
Tawada is associated with 1 patent: “Method, Device, and Medium for Bit-Width Reduction in Ising Model.” The invention adds an auxiliary spin to an Ising model and sets a new interaction coefficient between that spin and at least one existing spin. This produces a new model that can reduce the bit-width of interaction coefficients and external magnetic field coefficients.
Career Highlights
Tawada’s listed patent reflects work on improving the representation of Ising models, which describe systems through spins, interactions between spins, and external magnetic fields. The disclosed method uses an auxiliary spin to achieve bit-width reduction.
Collaborations
Tawada’s listed coworkers include Nozomu Togawa and Daisuke Oku. His work is associated with Waseda University.
Conclusion
Masashi Tawada’s patent focuses on reducing the bit-width of Ising model coefficients through the addition of an auxiliary spin, highlighting his contribution to computational methods for these models.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile