Masaru Kudo

Title: Masaru Kudo: Innovator in Non-Volatile Memory Circuits

Introduction

Masaru Kudo is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology, particularly in non-volatile memory circuits. With a total of 2 patents to his name, Kudo's work focuses on enhancing the efficiency and performance of memory devices.

Latest Patents

Kudo's latest patents include a non-volatile memory circuit and a semiconductor device designed to reduce energy consumption during data writing. The non-volatile memory circuit ensures a small size and low power consumption while maintaining stable write operations. It features a slave latch within an NVDFF, with magnetoresistive elements connected to it. The store operation writes information from the slave latch to the magnetoresistive elements before power interruption, while the restore operation reads the information back at the time of return. This technique is applicable to various non-volatile memory circuits.

The second patent, a semiconductor device, focuses on reducing the energy consumed when writing data to a nonvolatile storage section. It includes a write control circuit that compares the data stored in MTJ elements with that held in a slave latch. If the data matches, the write control circuit refrains from writing to the MTJ elements, thus conserving energy.

Career Highlights

Masaru Kudo is currently associated with Sony Corporation, where he continues to innovate in the field of semiconductor technology. His work has been instrumental in advancing memory circuit designs that prioritize efficiency and performance.

Collaborations

Kudo collaborates with Kimiyoshi Usami, contributing to the development of cutting-edge technologies in the semiconductor industry.

Conclusion

Masaru Kudo's contributions to non-volatile memory circuits and semiconductor devices highlight his role as a key innovator in the technology sector. His patents reflect a commitment to improving energy efficiency and performance in memory technologies.