Scarborough, ME, United States of America

Mark Rathmell

This inventor holds 1 USPTO granted patent. Top assignee: National Semiconductor Corporation. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mark Rathmell. Retrieved from https://idiyas.com/inventor/mark-rathmell

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Mark Rathmell and His Non-Volatile Memory Invention.

Introduction

Mark Rathmell is an inventor associated with Scarborough, Maine, and National Semiconductor Corporation. His work includes a patent for a non-volatile memory cell featuring an asymmetrical split gate.

Latest Patents

Rathmell is credited with 1 patent: “Non-volatile memory cell with asymmetrical split gate and related system and method.” The patent describes forming a control gate over a semiconductor substrate, depositing conductive material, and etching that material into spacers. At least one spacer serves as a floating gate in a memory cell. The method also describes configurations in which a spacer is removed or control gates are separated to create structures for multiple memory cells.

Career Highlights

Rathmell’s patent work is associated with National Semiconductor Corporation. The invention focuses on memory-cell structure and fabrication, using conductive spacers alongside control gates to form components of non-volatile memory cells.

Collaborations

Rathmell’s listed coworkers include Andre Paul Labonte and Jiankang Bu. Their names are associated with his professional and patent-related context.

Conclusion

Mark Rathmell’s patent describes a fabrication approach for asymmetrical split-gate non-volatile memory cells, reflecting his contribution to semiconductor memory technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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