Mark D Noll

Title: Mark D Noll: Innovator in Integrated Circuit Design

Introduction

Mark D Noll is a prominent inventor based in Santa Clara, CA (US). He has made significant contributions to the field of integrated circuit design, particularly through his innovative patent that addresses the complexities of layout constraints in large integrated circuits.

Latest Patents

Mark D Noll holds a patent titled "System and method for generating effective layout constraints for a computer system." This invention provides a computer-implemented method for deriving constraints that guide automatic integrated circuit layout. The system is designed to enhance the design of large integrated circuits with complex synchronous timing behavior. It includes a netlist data structure that represents a circuit configuration and static timing information. The method allows for the selection of specified circuit elements to generate layout constraints, identifying the most critical paths based on static timing information, and generating constraints that cover each specified circuit element. This innovative approach discards non-critical paths and duplicates, ensuring that only the most relevant critical paths are used for layout constraints.

Career Highlights

Mark D Noll has had a successful career at Synopsys, Inc., where he has been instrumental in advancing integrated circuit design technologies. His work has significantly impacted the efficiency and effectiveness of circuit layout processes.

Collaborations

Throughout his career, Mark has collaborated with notable colleagues, including Kenneth E Scott and Robert L Walker. These collaborations have contributed to the development of innovative solutions in the field of integrated circuit design.

Conclusion

Mark D Noll's contributions to integrated circuit design through his innovative patent demonstrate his expertise and commitment to advancing technology in this critical field. His work continues to influence the design and implementation of complex integrated circuits.