Menlo Park, CA, United States of America

Mani Azimi


 

Average Co-Inventor Count = 2.8

ph-index = 7

Forward Citations = 106(Granted Patents)


Location History:

  • Redwood City, CA (US) (1998 - 2001)
  • Menlo Park, CA (US) (2014 - 2018)

Company Filing History:


Years Active: 1998-2018

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12 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Mani Azimi

Introduction

Mani Azimi is a prominent inventor based in Menlo Park, California. He has made significant contributions to the field of technology, particularly in processor architecture and on-chip interconnects. With a total of 12 patents to his name, Azimi's work has had a substantial impact on the industry.

Latest Patents

One of his latest patents is titled "Instruction set for supporting wide scalar pattern matches." This invention involves a processor that includes an instruction decoder to receive an instruction with multiple operands. The execution unit performs a shift operation for data elements stored in a specified location, handling overflow efficiently to generate a final result. Another notable patent is the "Modular decoupled crossbar for on-chip router." This architecture, known as MoDe-X, supports 5-port routing for 2D mesh interconnects. It utilizes decoupled row and column sub-crossbar modules, reducing both area and power consumption compared to conventional designs.

Career Highlights

Mani Azimi is currently employed at Intel Corporation, where he continues to innovate and develop cutting-edge technologies. His work at Intel has positioned him as a key player in advancing processor and interconnect designs.

Collaborations

Throughout his career, Azimi has collaborated with talented individuals such as Naveen Cherukuri and Hariharan L Thantry. These collaborations have further enhanced the quality and impact of his inventions.

Conclusion

Mani Azimi's contributions to technology through his patents and work at Intel Corporation highlight his role as an influential inventor. His innovative designs continue to shape the future of processor architecture and on-chip interconnects.

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