This inventor holds 1 USPTO granted patent. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1999.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 1999
Title: Manabu Nakayama: Inventor of an Overcurrent-Reducing Output Circuit
Introduction
Manabu Nakayama is an inventor associated with Saga, Japan, and Kabushiki Kaisha Toshiba. His listed patent describes an output circuit designed to reduce overcurrent during changes in output voltage.
Latest Patents
Nakayama is credited with 1 patent: “Output circuit with output voltage controlled by current flow through an.” The circuit combines an input inverting buffer with an output transistor circuit that controls the output-terminal voltage. A current divider, controlled by the output-terminal voltage, diverts current from the buffer output to the output transistor. This design reduces overcurrent as the output voltage rises, helping prevent the ground voltage from floating upward and limiting noise.
Career Highlights
The available information associates Nakayama’s patent work with Kabushiki Kaisha Toshiba. His listed invention addresses output-circuit behavior and the prevention of voltage-related noise.
Collaborations
Naoki Itoh is identified as Nakayama’s coworker. The provided information does not specify whether Itoh collaborated on the patent.
Conclusion
Manabu Nakayama’s listed patent presents a circuit approach to controlling output voltage while reducing overcurrent and its associated noise.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile