This inventor holds 2 USPTO granted patents. Top assignee: Ecole Polytechnique Federale De Lausanne. Active years: 2019.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Location History:
- Jouxtens-Mézery, CH (2019)
- Jouxtens-Mezery, CH (2019)
Company Filing History:
Years Active: 2019
Title: Innovations of Luca Gaetano Amarù
Introduction
Luca Gaetano Amarù is an accomplished inventor based in Jouxtens-Mézery, Switzerland. He has made significant contributions to the field of logic circuit optimization, holding 2 patents that showcase his innovative approaches.
Latest Patents
Amarù's latest patents include a method for optimizing the implementation of logic circuits through majority logic synthesis. This method involves providing an interpretation of the logic circuit using three Boolean variable majority operators, which return a logic value assumed by more than half of the variables. The process includes various transformations to reduce the area of the logic circuit through reshaping and elimination procedures. Another notable patent focuses on Boolean logic optimization in Majority-Inverter Graphs (MIG). This framework utilizes directed acyclic graphs consisting of three-input majority nodes and regular/complemented edges. The proposed MIG Boolean methods exploit the error masking property of majority operators to simplify the graph while maintaining performance.
Career Highlights
Luca Gaetano Amarù is affiliated with the École Polytechnique Fédérale de Lausanne, where he continues to advance his research in logic optimization. His work has led to significant improvements in logic network depth and efficiency, particularly in ASIC flows.
Collaborations
Amarù has collaborated with notable colleagues in his field, including Giovanni De Micheli and Pierre-Emmanuel Julien Gaillardon. Their combined expertise contributes to the innovative research and development in logic circuit optimization.
Conclusion
Luca Gaetano Amarù's contributions to the field of logic circuit optimization through his patents and research at the École Polytechnique Fédérale de Lausanne highlight his role as a leading inventor in this domain.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
