Bloomington, MN, United States of America

Lien Lee

This inventor holds 2 USPTO granted patents. Top assignee: Cypress Semiconductor Corporation. Active years: 2004-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lien Lee. Retrieved from https://idiyas.com/inventor/lien-lee-l4c7f31c

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 2

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 2004-2006

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2 patents (USPTO):Explore Patents

Title: Lien Lee: Semiconductor Process Inventor

Introduction

Lien Lee is an inventor associated with Bloomington, Minnesota, and semiconductor manufacturing technology. The supplied information credits Lee with 2 patents and identifies Cypress Semiconductor Corporation as the company where Lee works.

Latest Patents

The provided patent information describes a gate etch process for making a semiconductor structure. The method etches an anti-reflective coating layer at a pressure of 10 millitorr or less, then etches a nitride layer using two plasma steps with different fluorine-to-carbon ratios. The first plasma’s F:C ratio is greater than the second’s.

The same gate etch process description was supplied twice, so it is presented here as one invention rather than as two distinct patent summaries.

Career Highlights

Lee’s listed work at Cypress Semiconductor Corporation connects the inventor’s career with semiconductor technology. The gate etch process focuses on controlling plasma conditions during the formation of semiconductor structures.

Collaborations

The supplied information names Chan-Lon Yang and Benjamin Schwarz as Lee’s coworkers. It does not specify their roles in the described patent or process.

Conclusion

Lien Lee’s listed patent work concerns a gate etch process that uses carefully differentiated plasma conditions, reflecting a focus on semiconductor manufacturing methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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