San Jose, CA, United States of America

Laurice Thorsen Earl

This inventor holds 1 USPTO granted patent. Top assignee: International Business Machines Corporation. Active years: 2000.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Laurice Thorsen Earl. Retrieved from https://idiyas.com/inventor/laurice-thorsen-earl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 7.0

ph-index = 1

Forward Citations = 244(Granted Patents)


Company Filing History:


Years Active: 2000

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1 patent (USPTO):Explore Patents

Title: Laurice Thorsen Earl: Innovating VLSI Design Rule Checking

Introduction: Laurice Thorsen Earl, an inventor based in San Jose, California, has made significant contributions to the field of design automation for VLSI (Very Large Scale Integration) technology. With a focus on enhancing the accuracy and reliability of design rule checking software, Earl's innovations have the potential to impact the development of semiconductor devices dramatically.

Latest Patents: Earl holds a patent for a "Method for verifying design rule checking software." This method involves using a generate-and-verify computer program that iteratively checks design rules described in a runset file. By employing repetitive passes and creating an association table of error shapes and boundary shapes, the methodology aims to ensure comprehensive testing of VLSI chips, verifying their compliance with specific fabrication processes. This meticulous verification process results in customized software inputs that enhance the efficiency of design rule checks.

Career Highlights: Laurice Thorsen Earl has established himself as a key player in the field through his work at the International Business Machines Corporation (IBM). His expertise in VLSI design verification software has enabled him to contribute to advanced technological solutions that streamline chip design processes. Earl's patent exemplifies his initiative in addressing complex challenges within the semiconductor industry.

Collaborations: Throughout his career, Earl has collaborated with notable colleagues, including William F. DeCamp and Jason Steven Minahan. Working alongside these professionals, he has contributed to innovations in design verification methodologies and the development of robust software solutions tailored for semiconductor manufacturing.

Conclusion: Laurice Thorsen Earl's innovative approach to verifying design rule checking software showcases his commitment to advancing VLSI technology. His contributions at IBM and the successful patent reflect his significant impact on the semiconductor industry, making his work crucial for the future of chip design and manufacturing. Earl’s endeavors continue to inspire fellow inventors and engineers as they navigate the complexities of modern technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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