Pohang, South Korea

Kyung Tae Do

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Pohang University of Science and Technology Foundation. Active years: 2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kyung Tae Do. Retrieved from https://idiyas.com/inventor/kyung-tae-do-rw9mm4je

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2011

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1 patent (USPTO):Explore Patents

Title: Innovations of Kyung Tae Do in Digital Circuit Design.

Introduction

Kyung Tae Do is a notable inventor based in Pohang, South Korea. He has made significant contributions to the field of digital circuit design, particularly in the area of timing modeling methods for latch-based subsystems. His innovative approach has the potential to streamline verification processes in digital circuit design.

Latest Patents

Kyung Tae Do holds a patent for a "Black box timing modeling method and computer system for latch-based subsystem." This patent provides a method for characterizing setup time arcs and clock-to-output delay arcs in digital circuits that include synchronous elements such as latches. The method allows for efficient verification of latch-based designs without the need to re-verify internal components, thereby reducing both verification time and model size.

Career Highlights

Kyung Tae Do is associated with the Postech Academy-Industry Foundation, where he applies his expertise in digital circuit design. His work focuses on enhancing the efficiency of timing modeling methods, which is crucial for the development of advanced digital systems.

Collaborations

Kyung Tae Do collaborates with colleagues such as Young Hwan Kim and Haeng Seon Son. Together, they contribute to the advancement of technologies in their field.

Conclusion

Kyung Tae Do's innovative work in timing modeling methods for digital circuits exemplifies the importance of efficiency in modern technology. His contributions are paving the way for advancements in latch-based design verification.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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