Company Filing History:
Years Active: 2003
Title: Innovations of Kumar Sudarshan in Low-Power Multiplier Design
Introduction
Kumar Sudarshan is an accomplished inventor based in Fremont, CA. He has made significant contributions to the field of circuit design, particularly in the development of low-power multiplier circuits. His innovative approach has led to advancements that enhance performance while minimizing energy consumption.
Latest Patents
Kumar holds a patent for a "Dual threshold voltage complementary pass-transistor logic implementation of a low-power, partitioned multiplier." This invention focuses on a new low-power, high-performance multiplier circuit design. It utilizes a modified, symmetrical Wallace tree structure that allows for selective power management in different parts of the multiplier. The design incorporates complementary pass-transistor logic (CPL) 3:2 carry save adders (CSAs) arranged in left and right arrays. These arrays can independently receive power, enabling them to be turned on and off without affecting each other. The merge block, which includes additional CPL CSAs, is configured to output the result of multiplication operations.
Career Highlights
Kumar is currently employed at Intel Corporation, where he continues to innovate in the field of circuit design. His work has been instrumental in developing technologies that push the boundaries of efficiency and performance in electronic devices.
Collaborations
Kumar has collaborated with notable colleagues, including Narsing Krishna Vijayrao and Chi Keung Lee. Their combined expertise has contributed to the success of various projects within the company.
Conclusion
Kumar Sudarshan's contributions to low-power multiplier design exemplify the impact of innovative thinking in technology. His patent reflects a commitment to enhancing performance while reducing energy consumption, marking him as a significant figure in the field of circuit design.