San Jose, CA, United States of America

Krishnaraj Venkatesan

This inventor holds 1 USPTO granted patent. Top assignee: Marvell Asia Pte., Ltd.. Active years: 2023.


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1


Company Filing History:


Years Active: 2023

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1 patent (USPTO):Explore Patents

Title: Innovations by Krishnaraj Venkatesan

Introduction

Krishnaraj Venkatesan is an accomplished inventor based in San Jose, CA. He has made significant contributions to the field of electronic design automation, particularly in the area of test access mechanisms.

Latest Patents

One of his notable patents is titled "System and methods for IJTAG reduced access time in a hierarchical design." This patent describes a system that includes a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registries (TDR). The system features a plurality of hierarchical electronic components, each equipped with a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register. The D-SIB register is designed to prevent access to its associated TDR when a reset signal is asserted, while the A-SIB register allows access to its subsequent A-SIB or D-SIB register when the reset signal is asserted. Krishnaraj holds 1 patent in total.

Career Highlights

Krishnaraj Venkatesan is currently employed at Marvell Asia Pte., Ltd., where he continues to innovate and develop advanced electronic systems. His work has been instrumental in enhancing the efficiency of electronic testing processes.

Collaborations

He collaborates with various professionals in the field, including his coworker Raghuveer Shivaraj, to drive forward innovative solutions in electronic design.

Conclusion

Krishnaraj Venkatesan's contributions to the field of electronic design automation exemplify the impact of innovative thinking in technology. His patent on IJTAG access mechanisms showcases his commitment to improving electronic testing methodologies.

Profile summary based on public USPTO records.
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