Sendai, Japan

Ko Yoshikawa

This inventor holds 1 USPTO granted patent. Top assignee: Tohoku University. Active years: 2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ko Yoshikawa. Retrieved from https://idiyas.com/inventor/ko-yoshikawa-t1xvk6kf

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2024

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1 patent (USPTO):Explore Patents

Title: Ko Yoshikawa - Innovator in Semiconductor Circuit Design

Introduction

Ko Yoshikawa is a prominent inventor based in Sendai, Japan. He has made significant contributions to the field of semiconductor circuit design, showcasing his expertise through innovative patents.

Latest Patents

Yoshikawa holds a patent for a semiconductor circuit and support device for logic circuit design. This invention includes a first clock gating circuit that outputs a gated clock signal, a non-volatile flip-flop, an acquisition circuit for data input, and a power gating circuit that controls electric power supply based on enable signals.

Career Highlights

Ko Yoshikawa is affiliated with Tohoku University, where he continues to advance research in semiconductor technologies. His work has been instrumental in enhancing the efficiency and functionality of logic circuits.

Collaborations

Throughout his career, Yoshikawa has collaborated with notable colleagues, including Yitao Ma and Tetsuo Endoh. These partnerships have fostered innovation and contributed to the development of cutting-edge technologies in the semiconductor field.

Conclusion

Ko Yoshikawa's contributions to semiconductor circuit design exemplify his dedication to innovation. His patent reflects a commitment to advancing technology, making him a valuable figure in the field of electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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