Hyogo, Japan

Kiyotaka Ishibushi

This inventor holds 1 USPTO granted patent. Top assignee: Ricoh Company, Ltd.. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kiyotaka Ishibushi. Retrieved from https://idiyas.com/inventor/kiyotaka-ishibushi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Kiyotaka Ishibushi and Semiconductor Manufacturing Innovation.

Introduction

Kiyotaka Ishibushi is an inventor associated with Ricoh Company, Ltd., and is listed in connection with a patent for a method of manufacturing a semiconductor device. His recorded patent activity includes 1 patent.

Latest Patents

Ishibushi’s listed patent, “Method of Manufacturing Semiconductor Device,” describes a process for patterning a semiconductor wafer. The wafer’s main surface is divided into a device chip area, a surrounding peripheral area, and a blank area between them. The method coats the surface with positive photosensitive resist, defines an additional exposure area in the blank area, and applies separate exposure processes to the peripheral and additional exposure areas and to the device chip area. After selected resist is removed to form a pattern, that pattern serves as a mask for dry-etching the wafer surface.

Career Highlights

The available information connects Ishibushi’s work to semiconductor-device manufacturing and Ricoh Company, Ltd. His patent focuses on coordinating exposure and resist-patterning steps across distinct wafer regions.

Collaborations

Ishibushi’s listed coworkers include Tohru Haruki and Tadao Uehara. The provided information does not specify their roles in the patent or the nature of their collaboration.

Conclusion

Kiyotaka Ishibushi’s recorded invention addresses semiconductor wafer processing through a structured exposure, resist-patterning, and dry-etching method.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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