Ebina, Japan

Kiyoshi Takaoki

This inventor holds 1 USPTO granted patent. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1988.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kiyoshi Takaoki. Retrieved from https://idiyas.com/inventor/kiyoshi-takaoki-y60vtocr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 21(Granted Patents)


Company Filing History:


Years Active: 1988

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1 patent (USPTO):Explore Patents

Title: Kiyoshi Takaoki: Innovator in Semiconductor Manufacturing

Introduction

Kiyoshi Takaoki is a notable inventor based in Ebina, Japan. He has made significant contributions to the field of semiconductor manufacturing, particularly through his innovative methods that enhance device fabrication.

Latest Patents

Takaoki holds a patent for a method of manufacturing a semiconductor device involving a sidewall spacer. This method allows for the creation of submicron patterns in semiconductor devices. The process includes forming a p-type semiconductor layer on an n-type substrate, followed by the application of insulating films. A first mask layer is created, which is then patterned to achieve finer details than the original resist. This innovative approach is crucial for advancing semiconductor technology.

Career Highlights

Kiyoshi Takaoki is associated with Kabushiki Kaisha Toshiba, a leading company in the technology sector. His work has been instrumental in developing advanced semiconductor manufacturing techniques that are essential for modern electronics.

Collaborations

Takaoki has collaborated with notable colleagues such as Hitoshi Tsuji and Tiharu Kato. Their combined expertise has contributed to the success of various projects within the semiconductor industry.

Conclusion

Kiyoshi Takaoki's contributions to semiconductor manufacturing exemplify the importance of innovation in technology. His patented methods continue to influence the development of advanced electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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