logo

For the Inventor, By the Inventor

Round Rock, TX, United States of America

Kimberly Marie Fernsler

This inventor holds 21 USPTO granted patents and 5 published patent applications, primarily in Processor Management. Top assignees: International Business Machines Corporation, Kabushiki Kaisha Toshiba. Active years: 2007-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kimberly Marie Fernsler. Retrieved from https://idiyas.com/inventor/kimberly-marie-fernsler

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 21 

% Patents Active = 52.4

Average Co-Inventor Count = 4.4

ph-index = 4

Forward Citations = 155(Granted Patents)


Location History:

  • Round Rock, TX (US) (2007 - 2014)
  • Cedar Park, TX (US) (2018 - 2023)

Company Filing History:

goldMedal21 out of 166,483 
 
International Business Machines Corporation
 patents
silverMedal1 out of 53,315 
 
Kabushiki Kaisha Toshiba
 patents
where one patent can have more than one assignee

Years Active: 2007-2025

Loading Chart...
Areas of Expertise:
Buffer Management
Load Instructions
Cache Mechanisms
Data Synchronization
Out-of-Order Processing
Processor Systems
Dynamic Management
Address Translation
Memory Access
High Frequency Processors
Sequential Load Consistency
Page Size Prediction
21 patents (USPTO):Explore Patents
1. 12411688 - Gather buffer management for unaligned and gather load operations (2025-09-09),
2. 11755324 - Gather buffer management for unaligned and gather load operations (2023-09-12),
3. 11687337 - Processor overriding of a false load-hit-store detection (2023-06-27),
4. 11379241 - Handling oversize store to load forwarding in a processor (2022-07-05),
5. 11321088 - Tracking load and store instructions and addresses in an out-of-order processor (2022-05-03),
6. 11314510 - Tracking load and store instructions and addresses in an out-of-order processor (2022-04-26),
7. 11263151 - Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations (2022-03-01),
8. 10884740 - Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads (2021-01-05),
9. 10564978 - Operation of a multi-slice processor with an expanded merge fetching queue (2020-02-18),
10. 10037211 - Operation of a multi-slice processor with an expanded merge fetching queue (2018-07-31),
11. 9916245 - Accessing partial cachelines in a data cache (2018-03-13),
12. 8898667 - Dynamically manage applications on a processing system (2014-11-25),
13. 8387050 - System and method to dynamically manage applications on a processing system (2013-02-26),
14. 7769985 - Load address dependency mechanism system and method in a high frequency, low power processor system (2010-08-03),
15. 7739477 - Multiple page size address translation incorporating page size prediction (2010-06-15),

Title: **Kimberly Marie Fernsler: Innovator in Processor Technology**

Introduction

Kimberly Marie Fernsler is a prominent inventor located in Round Rock, TX, with a remarkable portfolio of 20 patents. Her work primarily focuses on advancements in computer architecture and processor operations, showcasing her dedication to innovative solutions in technology.

Latest Patents

Among her latest patents is a groundbreaking invention titled "Gather Buffer Management for Unaligned and Gather Load Operations." This invention encompasses a computer system, processor, and programming instructions designed to optimize gather buffer management in processing unaligned load operations. The processor core's processing pipeline incorporates execution units that process unaligned load instructions in two distinct phases, improving efficiency in data retrieval and processing.

Another notable patent is "Processor Overriding of a False Load-Hit-Store Detection," which presents a method for refining processor core operations. This patent details how an initially rejected load instruction can be transformed with a warning label to bypass a false load-hit-store detection, enhancing overall processing accuracy and speed.

Career Highlights

Kimberly has had significant contributions to major corporations, including IBM and Kabushiki Kaisha Toshiba. Her experience in these renowned companies has undoubtedly enriched her expertise in both processor technology and innovation.

Collaborations

Throughout her career, Kimberly has collaborated with distinguished colleagues, such as David Allen Hrusecky and Bryan J Lloyd. Their teamwork has led to the development of advanced technologies and innovations that push the boundaries of current computer systems.

Conclusion

Kimberly Marie Fernsler stands as a testament to the power of innovation in technology. Her extensive list of patents and contributions to major corporations illustrates her commitment to advancing processor technology, making her a noteworthy figure in the field of engineering.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…