Kimberly K Van Vliet

Title: Kimberly K. Van Vliet and Circuit-Network Testing

Introduction

Kimberly K. Van Vliet is an inventor associated with Charlotte, North Carolina, and International Business Machines Corporation. Her listed patent concerns testing circuit networks that combine integrated circuits using different boundary-testing approaches.

Latest Patents

The provided information lists 1 patent for Van Vliet: “System and Method for Testing a Circuit Network Having Elements Testable.” The invention describes a system and method for boundary testing a circuit network assembled from integrated circuit chips on a printed circuit card or board. It addresses networks containing chips that support IEEE 1149.1 boundary testing alongside chips that support Level Sensitive Scan Design boundary testing but not IEEE 1149.1.

The described test system includes a test access port interface and controller, with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset inputs and outputs. It also includes an instruction register, a bypass register, a test clock generator, and a Level Sensitive Scan Device boundary scan register.

Career Highlights

The available details connect Van Vliet’s patent work with IBM and the development of testing methods for circuit networks containing different types of testable integrated circuits. The patent’s approach brings these testing capabilities together within a single test system.

Collaborations

William F. Heybruck and Andres M. Molina are identified as Van Vliet’s coworkers. The supplied information does not specify their roles in the patent or describe particular collaborative projects.

Conclusion

Kimberly K. Van Vliet’s listed invention addresses the practical challenge of testing circuit networks that combine IEEE 1149.1 and Level Sensitive Scan Design boundary-testing technologies.