Kalispell, MT, United States of America

Kert L Dolechek

This inventor holds 18 USPTO granted patents, primarily in Semiconductor Processing. Top assignee: Semitool, Inc.. Active years: 2001-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kert L Dolechek. Retrieved from https://idiyas.com/inventor/kert-l-dolechek

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 44.4

Average Co-Inventor Count = 1.8

ph-index = 8

Forward Citations = 591(Granted Patents)


Company Filing History:


Years Active: 2001-2011

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Areas of Expertise:
Semiconductor Workpiece
Wafer Thinning
Wafer Cleaning
Cross Flow Processor
Automated Processing
Fluid Heating
Chemical Solutions
Wafer Input/Output
Processing Apparatus
Cleaning System
Semiconductor Materials
Processing Techniques
18 patents (USPTO):Explore Patents

Title: Kert L Dolechek: Innovator in Semiconductor Technology

Introduction

Kert L Dolechek is a prominent inventor based in Kalispell, MT (US), known for his significant contributions to semiconductor technology. With a total of 18 patents to his name, Dolechek has made remarkable advancements in the processing of semiconductor workpieces. His innovative approaches have led to improved efficiency and yields in semiconductor manufacturing.

Latest Patents

Dolechek's latest patents include groundbreaking inventions such as a method and apparatus for processing semiconductor workpieces. This invention allows for the production of thinner workpieces while maintaining their strength. The apparatus features a chuck that includes a body, a retainer, and a seal forming member. When a workpiece is placed on the chuck body, the retainer engages to cover the peripheral portion of the back side, while exposing the interior region. This design enables a wet chemical etching process that thins the workpiece and forms a thick rim of semiconductor material, enhancing the workpiece's strength.

Another notable patent is the process and apparatus for thinning a semiconductor workpiece. This system allows for the production of thinner wafers that are less susceptible to breaking. The unique structure improves handling and reduces processing steps, resulting in enhanced yields and process efficiency.

Career Highlights

Dolechek has built a successful career at Semitool, Inc., where he has

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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