Seoul, South Korea

Keonhee Cho

USPTO Granted Patents = 5 

Average Co-Inventor Count = 3.8

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2023-2025

where 'Filed Patents' based on already Granted Patents

5 patents (USPTO):

Title: The Innovative Mind of Keonhee Cho

Introduction

Keonhee Cho is a prominent inventor based in Seoul, South Korea. He has made significant contributions to the field of integrated circuits and memory technology. With a total of four patents to his name, Cho's work reflects his dedication to advancing electronic design and functionality.

Latest Patents

One of his latest patents is the "Dual-edge-triggered flip-flop." This invention includes an input logic circuit, a first latch, a second latch, and an output multiplexer. The input logic circuit outputs a clock bar signal based on an input data bit and a clock signal. The first and second latches operate based on the input data bit, the clock signal, and the clock bar signal. The output multiplexer operates based on outputs from nodes of the first and second nodes, ultimately producing an output data bit. Notably, the input logic circuit maintains a uniform value during periods without changes in the output data bit.

Another significant patent is the "Integrated circuit including cell array with word line assist cells." This integrated circuit features a cell array comprising multiple memory cells arranged in several first columns, along with word line assist cells in at least one second column. A plurality of word lines extends across the first rows of the cell array, connecting to both the memory cells and the word line assist cells. A row driver is configured to drive these word lines, enhancing the circuit's performance.

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