This inventor holds 1 USPTO granted patent. Top assignees: Sanyo Electric Co., Ltd., Tokyo Sanyo Electric Co.. Active years: 1986.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
1 out of 8,782 
1 out of 69 Years Active: 1986
Title: Keizo Mori: Inventor of a Balanced MIS Capacitor
Introduction
Keizo Mori is an inventor associated with Gunma, Japan. His recorded patent work concerns a capacitor design intended to maintain balanced electrical impedance despite parasitic capacitance.
Latest Patents
Mori’s listed patent, “Capacitor Produced of a Layer Combination of Metal, Insulator and,” describes two capacitor elements with metal-insulator-semiconductor (MIS) structures. The elements are connected in a zigzag arrangement to create a balanced parallel connection. The patent also describes a circuit with two balanced impedance branches bridged by the capacitor, helping the branches remain balanced regardless of parasitic capacitance. Mori is credited with 1 patent in the supplied data.
Career Highlights
The available information associates Mori with Sanyo Electric Co., Ltd. and Tokyo Sanyo Electric Co. His patent reflects work on capacitor construction and circuit balance.
Collaborations
Mori’s listed coworkers include Hiroyasu Kishi and Yuji Kimoto.
Conclusion
Keizo Mori’s recorded invention focuses on a balanced MIS capacitor designed to help preserve circuit impedance balance in the presence of parasitic capacitance.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile