Kawasaki, Japan

Kazuyoshi Kanei

This inventor holds 2 USPTO granted patents. Top assignee: Fujitsu Corporation. Active years: 2005-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kazuyoshi Kanei. Retrieved from https://idiyas.com/inventor/kazuyoshi-kanei

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 50.0

Average Co-Inventor Count = 6.9

ph-index = 1

Forward Citations = 25(Granted Patents)


Location History:

  • Yokohama, JP (2005)
  • Kawasaki, JP (2011)

Company Filing History:


Years Active: 2005-2011

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2 patents (USPTO):Explore Patents

Title: Kazuyoshi Kanei: Innovator in Power Supply Noise Analysis

Introduction

Kazuyoshi Kanei is a notable inventor based in Kawasaki, Japan. He has made significant contributions to the field of electrical engineering, particularly in power supply noise analysis. With a total of 2 patents, his work focuses on simplifying complex processes in circuit board design and analysis.

Latest Patents

Kanei's latest patents include a "Power Supply Noise Analysis Model Generating Method" and a "Power Supply Noise Analysis Model Generating Apparatus." The objective of these inventions is to simplify the power supply noise analysis model of a circuit board. By obtaining CAD data from a CAD apparatus, overlapping power supply islands among different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in this extracted power supply pair, and the nodes are projected onto the corresponding power supply islands. A mesh region is determined for each power supply island, and the impedance (L, R, C) between nodes is calculated. This leads to the creation of a power supply noise analysis model based on the impedance between nodes in each layer and the capacitance between layers.

Another significant invention is the "Noise Checking Method and Apparatus." This invention aims to enhance the accuracy of noise calculations and checks during electronic circuit design. The noise checking apparatus includes a model production section for creating a simulation model of a circuit portion related to a specific wiring line. It also features a simulation section that calculates signal and noise waveforms, a noise waveform synthesis section for combining these waveforms, and a noise checking section for performing noise checks based on the synthesized waveforms.

Career Highlights

Kazuyoshi Kanei is currently employed at Fujitsu Corporation, where he continues to innovate in the field of electrical engineering. His work has been instrumental in improving the efficiency and accuracy of noise analysis in electronic circuits.

Collaborations

Kanei has collaborated with notable coworkers such as Yoshiyuki Iwakura and Toshiro Sato, contributing to advancements in their shared field of expertise.

Conclusion

Kazuyoshi Kanei's contributions to power supply noise analysis have made a significant impact on the field of electrical engineering. His innovative patents reflect his commitment to enhancing the efficiency and accuracy of circuit design processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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