Austin, TX, United States of America

Kaushik Viswanathan

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Nvidia Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kaushik Viswanathan. Retrieved from https://idiyas.com/inventor/kaushik-viswanathan-4xj3bui4

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Kaushik Viswanathan: Inventor in Clock and Power-Supply Circuitry

Introduction

Kaushik Viswanathan is an inventor based in Austin, Texas, and is associated with NVIDIA Corporation. His patent work addresses circuit techniques for improving operation under challenging power-supply conditions.

Latest Patents

Viswanathan is named on one patent, titled “Clock Stretching Circuit for Minimum Operating Voltage Improvement.” The invention concerns circuits designed to mitigate noise and voltage droop on supply rails. It uses a clock stretcher with a chain of adjustable delay elements to generate multiple phases of a clock signal. The circuit selects among those phases to produce a stretched, glitchless version of the original clock signal. This approach is intended to support improved minimum operating voltage performance. His reported patent count is 1 patent.

Career Highlights

Viswanathan’s listed patent work focuses on clock control and power integrity, particularly techniques for managing supply-rail noise and droop. He is associated with NVIDIA Corporation.

Collaborations

Daniel Rodriguez and Tezaswi Raja are identified as some of Viswanathan’s coworkers. Their shared professional association provides context for his work at NVIDIA, though no specific collaboration on the patent is established by the information provided.

Conclusion

Kaushik Viswanathan’s patent illustrates an engineering approach to clock stretching that aims to help circuits operate reliably amid supply-voltage noise and droop.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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