Santa Clara, CA, United States of America

Kaushik Narayanun


Average Co-Inventor Count = 3.7

ph-index = 1

Forward Citations = 6(Granted Patents)


Location History:

  • San Jose, CA (US) (2020)
  • Santa Clara, CA (US) (2021 - 2022)
  • Los Gatos, CA (US) (2023)

Company Filing History:


Years Active: 2020-2023

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4 patents (USPTO):

Title: Innovations by Kaushik Narayanun

Introduction

Kaushik Narayanun is a prominent inventor based in Santa Clara, CA. He has made significant contributions to the field of circuit design and testing, holding a total of 4 patents. His work focuses on improving the accuracy and efficiency of testing complex circuit designs.

Latest Patents

Kaushik's latest patents include innovative techniques that enhance the testing process for circuit designs. One of his notable patents is titled "Deep learning based identification of difficult to test nodes." This invention introduces techniques to improve the accuracy and speed of detecting and remediating difficult-to-test nodes in a circuit design netlist. The methods utilize improved netlist representations, test point insertion, and trained neural networks to achieve better results.

Another significant patent is "Controlling test networks of chips using integrated processors." This disclosure presents a solution that employs test processors to offer greater flexibility compared to existing DFX blocks used for controlling test networks in chips. The test processors can be programmed at any time, even after manufacturing, allowing for support of virtually unlimited core chips in any configuration. This flexibility reduces the engineering effort required in design and verification, accelerates schedules, and may prevent additional tapeouts in case of DFX design bugs. By simplifying debug and diagnosis, the time-to-market timeline can be significantly shortened.

Career Highlights

Kaushik Narayanun is currently employed at Nvidia Corporation, where he continues to innovate and contribute to advancements in chip design and testing methodologies. His work has had a profound impact on the efficiency and effectiveness of circuit testing.

Collaborations

Some of his notable coworkers include Harbinder Sikka and Lijuan Luo, who collaborate with him on various projects at Nvidia Corporation.

Conclusion

Kaushik Narayanun's contributions to the field of circuit design and testing are noteworthy. His innovative patents reflect his commitment to enhancing the efficiency and accuracy of testing processes in the semiconductor industry.

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