The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Nov. 05, 2020
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Kaushik Narayanun, Santa Clara, CA (US);

Mahmut Yilmaz, Santa Clara, CA (US);

Shantanu Sarangi, Santa Clara, CA (US);

Jae Wu, Santa Clara, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/333 (2020.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 30/394 (2020.01); G06F 30/323 (2020.01); G06F 115/12 (2020.01); G06F 115/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G01R 31/31704 (2013.01); G01R 31/318583 (2013.01); G06F 30/394 (2020.01); G06F 30/323 (2020.01); G06F 2115/02 (2020.01); G06F 2115/12 (2020.01);
Abstract

The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.


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