Baltimore, MD, United States of America

Kathryn Arpino

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Johns Hopkins University. Active years: 2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kathryn Arpino. Retrieved from https://idiyas.com/inventor/kathryn-arpino

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2014

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1 patent (USPTO):Explore Patents

Title: Kathryn Arpino: Innovator in Semiconductor Technology

Introduction

Kathryn Arpino is a notable inventor based in Baltimore, MD (US). She has made significant contributions to the field of semiconductor technology, particularly through her innovative patent.

Latest Patents

Kathryn holds a patent for "Simplified devices utilizing novel pn-semiconductor structures." This invention involves an electronic or electro-optic device that includes a p-type semiconductor layer and an n-type semiconductor layer, which together form a p-n junction. The device features electrical leads connected to these semiconductor layers, with at least one layer incorporating a doped topological-insulator material that has an electrically conducting surface.

Career Highlights

Kathryn is affiliated with Johns Hopkins University, where she continues to advance her research and development in semiconductor technologies. Her work has garnered attention for its potential applications in various electronic devices.

Collaborations

Some of her notable coworkers include Patrick Cottingham and John P. Sheckelton, who have collaborated with her on various projects within the university.

Conclusion

Kathryn Arpino's contributions to semiconductor technology exemplify her innovative spirit and dedication to advancing the field. Her patent reflects her expertise and commitment to developing cutting-edge solutions in electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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