This inventor holds 1 USPTO granted patent. Top assignee: National Tsing Hua University. Active years: 2006.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2006
Title: Innovations of Kao-Liang Cheng
Introduction
Kao-Liang Cheng is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of memory testing through his innovative methods. His work is particularly recognized for enhancing the efficiency of multi-port memory testing.
Latest Patents
Cheng holds a patent for a "Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction." This method involves generating test clock signals with the same frequency but different delay periods to control memory access through various access ports. The approach allows for consecutive memory operations to be conducted in a folded sequence, ensuring that all operations are completed within the same test clock cycle.
Career Highlights
Kao-Liang Cheng is affiliated with National Tsing Hua University, where he continues to advance research in memory technologies. His innovative methods have the potential to significantly reduce testing time, making them valuable in the field of electronics.
Collaborations
Cheng has collaborated with esteemed colleagues such as Cheng-Wen Wu and Chih-Tsun Huang. Their joint efforts contribute to the ongoing advancements in memory testing methodologies.
Conclusion
Kao-Liang Cheng's contributions to memory testing represent a significant advancement in the field. His innovative patent showcases his commitment to improving technology and efficiency in electronic memory systems.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile